The present application relates generally to semiconductor devices and includes methods and structures for correcting flare effect induced error of mask patterns.
To transfer an integrated circuit pattern onto a layer of a semiconductor device (for example, a semiconductor wafer), a mask pattern sometimes referred to as a photo mask is designed first. The pattern on the mask pattern is then transferred to a layer (for example, a photo resist layer) of the semiconductor device by performing a lithography process (for example, a photolithographic process).
As the design pattern of integrated circuits becomes smaller and the mask pattern becomes of higher density in its pattern arrangement, stray light from nearby openings in the mask, particles in the mask, or defects in a lens between the mask and the layer of the semiconductor device contribute to an error between a target dimension and an actual dimension in a patterned feature referred to as a flare induced error. Thus, the critical dimension (CD) of the pattern may vary from the intended target size due to the flare induced error.